Symbolic Resonance Array (SRA) — Technical FAQ for Engineers

1) What is the SRA?

The Symbolic Resonance Array (SRA) is a patent-pending analog neuromorphic architecture that performs low-power symbolic computation using coupled phase-transition pillar elements (VO₂). Each element participates in a controlled excite → relax → read cycle; the coupled system settles into stable attractor patterns that are digitized as symbol vectors for downstream use.

2) What does “analog resonance + symbol vectors” mean?

Analog resonance: Neighboring pillars are driven in a sub-threshold regime near the insulator–metal transition so that interactions synchronize into repeatable modes without forcing hard switching.
Symbol vectors: The stabilized multi-pillar state is measured (e.g., ΔR features, relaxation constants, simple synchronization indices) and quantized into a fixed-length vector. This is a physical representation of discrete state, not a numerical neuron simulation.

Implementation details in materials, circuits, reliability, and noise tolerance are non-trivial. They’re handled through explicit simulation and bring-up plans before and during fabrication.

3) Current readiness

Device concept, operating cycle, array topology, and readout scheme are specified to begin US microfabrication process development.
Simulation framework (thermal–electrical FEM, stochastic/Monte-Carlo error modeling, information-theoretic lower bounds) is defined and tied to measurable lab parameters for conservative, pre-silicon estimates.
A first-lot process flow using standard VO₂ thin-film deposition, lithography, metallization, and bench packaging is outlined.

4) Energy expectations (pre-silicon)

Order-of-magnitude projections place SRA switching/encoding energy in the ~1–10 fJ per symbol range under sub-threshold resonance, versus ~10–100 fJ per bit typical for advanced CMOS toggling. These are conservative and pending experimental validation. The projected advantage comes from: no global clocking/refresh, localized threshold excitations, and intrinsic analog gain that reduces continuous drive.

5) Throughput and reliability (pre-silicon)

Stability window: Simulations identify safe voltage–time envelopes where pillars remain below the hard IMT but still converge to stable modes suitable for symbolization.
Error behavior: Monte-Carlo studies (noise, variability, drift, cross-talk) produce low per-pillar symbol error rates with straightforward threshold calibration.
Scaling: Arrays show predictable improvements in symbols/joule and vector throughput up to a practical coupling “sweet spot” before diminishing returns; redundancy and calibration maintain yield.

All published/internally shared rates are lower-bound estimates computed from empirical-style symbol histograms and error probabilities (i.e., conservative by design).

6) Materials and processes

Material: VO₂ thin films or micro-pillars on Si, sapphire, or glass (specific dopants/anneals held under NDA).
Deposition (examples): reactive sputter, PLD, or ALD with controlled post-anneal.
Patterning: standard MEMS/lithography; pillar geometry can be cylindrical or tapered (finite tip radius).
Metals: conventional adhesion + noble stacks; final choice set by contact resistance and thermal stability.
Packaging: research-die level for bench bring-up; excite/read access to each module.

No exotic or impractical fab steps are required for a first lot.

7) Device architecture and cycle

Module: symmetric multi-pillar cluster (e.g., eight-element ring or lattice) with engineered coupling.
Excite: short, sub-threshold pulses initiate partial domain reconfiguration.
Relax: thermal/electrical coupling drives convergence to a coherent pattern.
Read: sample the stabilized state over a defined window and quantize to a symbol vector.
Interface: simple mixed-signal front-end plus ADC capture; no proprietary toolchain is required for initial tests.

8) Prototype roadmap (first lot)

Phase A — Films & coupons
• VO₂ deposition splits (thickness/anneal/O₂) on chosen substrates.
• Coupons for Tc, sheet-R, contact tests; XRD/Raman/AFM as available.

Phase B — Pillars & contacts
• Lithography for pillar geometry and interconnect.
• VO₂ definition by etch or lift-off per foundry preference.
• Contact chain test structures; Ti/Pt or Ti/Au candidates.

Phase C — Bring-up
• Excite → relax → read sweeps to map stable operating regions.
• Noise/temperature/aging sweeps to characterize margins.

Phase D — Iterate
• Tighten Tc, contact-R, and coupling geometry; prepare a pilot array for extended testing.

9) What data do partners produce?

Process travelers and split matrices.
Wafer-level metrology maps (Tc, sheet-R, thickness uniformity).
Electrical data for coupons and contact chains.
Module-level excite/relax/read datasets are sufficient to compute symbol histograms, error rates, and conservative throughput.
Packaging notes and handling guidance.

10) Known risks and mitigations

Thermal uniformity: layout + local heating control, verified via FEM and tested in environmental sweeps.
Contact drift: noble stacks, interface prep, and contact chain monitoring.
Variability & drift: per-pillar calibration and adaptive thresholds.
Cross-talk & noise: pulse shaping and spacing informed by modeled coupling matrices; shielding where needed.
Aging: accelerated cycling tests included in bring-up.

All are covered in the simulation plan and reflected in the first-lot test matrix.

11) Integration path

Output is a fixed-length digital symbol vector captured by standard ADC/logic. The SRA can function as:

Low-energy pre-processor for embedded AI or sensing,
Symbolic co-processor for control loops and anomaly detection, or
A hybrid VO₂–CMOS in-memory symbolic block with straightforward firmware.

12) Engagement & IP

IP is owned by Theresa M. Kelly / Mirrorseed Project (provisional filed; non-provisional in preparation).
NDAs cover process parameters, mask details, and claim-sensitive content.
Licensing discussions open after non-provisional filing and initial hardware results.

13) Who should contact Mirrorseed

U.S. microfab partners with phase-transition oxide experience (or willingness to run VO₂ under standard controls), mixed-signal test capability, and R&D flexibility for one or two focused iterations.

Contact: info@mirrorseed.org: include deposition methods, etch/lift-off options, contact stacks, packaging services, and typical R&D lead times.